Version 4.1 SHEET 1 3372 1232 WIRE 384 -368 352 -368 WIRE 496 -368 464 -368 WIRE 688 -368 560 -368 WIRE -768 -352 -800 -352 WIRE -496 -352 -768 -352 WIRE -368 -352 -416 -352 WIRE -240 -352 -368 -352 WIRE -160 -352 -240 -352 WIRE 80 -352 -160 -352 WIRE 80 -336 80 -352 WIRE -800 -288 -800 -352 WIRE -368 -288 -368 -352 WIRE -240 -288 -240 -352 WIRE 1376 -272 992 -272 WIRE 80 -224 80 -256 WIRE 144 -224 144 -256 WIRE 144 -224 80 -224 WIRE 192 -224 144 -224 WIRE 352 -224 352 -368 WIRE 352 -224 272 -224 WIRE 400 -224 352 -224 WIRE 992 -224 992 -272 WIRE 688 -208 688 -368 WIRE 688 -208 576 -208 WIRE 736 -208 688 -208 WIRE 80 -176 80 -224 WIRE 576 -144 576 -208 WIRE 400 -128 352 -128 WIRE 352 -96 352 -128 WIRE -800 -16 -800 -208 WIRE -512 -16 -800 -16 WIRE -368 -16 -368 -224 WIRE -368 -16 -512 -16 WIRE -240 -16 -240 -208 WIRE -240 -16 -368 -16 WIRE 80 16 80 -96 WIRE 352 16 352 -16 WIRE 352 16 80 16 WIRE 576 16 576 -64 WIRE 576 16 352 16 WIRE 848 16 576 16 WIRE 992 16 992 -144 WIRE 992 16 848 16 WIRE -512 32 -512 -16 WIRE 848 80 848 16 WIRE 336 368 304 368 WIRE 448 368 416 368 WIRE 640 368 512 368 WIRE -768 384 -800 384 WIRE -672 384 -768 384 WIRE -448 384 -592 384 WIRE -352 384 -448 384 WIRE -224 384 -352 384 WIRE -208 384 -224 384 WIRE 32 384 -208 384 WIRE 32 400 32 384 WIRE -800 448 -800 384 WIRE -448 448 -448 384 WIRE -224 448 -224 384 WIRE -352 464 -352 384 WIRE 1360 464 944 464 WIRE 32 512 32 480 WIRE 96 512 96 480 WIRE 96 512 32 512 WIRE 144 512 96 512 WIRE 304 512 304 368 WIRE 304 512 224 512 WIRE 352 512 304 512 WIRE 944 512 944 464 WIRE 640 528 640 368 WIRE 640 528 528 528 WIRE 688 528 640 528 WIRE 32 560 32 512 WIRE 528 592 528 528 WIRE -352 608 -352 544 WIRE 352 608 304 608 WIRE 304 640 304 608 WIRE -800 720 -800 528 WIRE -560 720 -800 720 WIRE -448 720 -448 512 WIRE -448 720 -560 720 WIRE -352 720 -352 672 WIRE -352 720 -448 720 WIRE -224 720 -224 528 WIRE -224 720 -352 720 WIRE 32 752 32 640 WIRE 304 752 304 720 WIRE 304 752 32 752 WIRE 528 752 528 672 WIRE 528 752 304 752 WIRE 800 752 528 752 WIRE 944 752 944 592 WIRE 944 752 800 752 WIRE -560 768 -560 720 WIRE 800 816 800 752 FLAG -160 -352 power_supply_output FLAG 848 80 0 FLAG -512 32 0 FLAG -768 -352 Vin FLAG 736 -208 error FLAG 1376 -272 development_loop_out FLAG 144 -256 pot_divided FLAG 400 -224 inv FLAG 400 -128 non_inv FLAG -208 384 power_supply_output-1 FLAG 800 816 0 FLAG -560 768 0 FLAG -768 384 Vin-1 FLAG 688 528 error-1 FLAG 1360 464 finished_loop_out FLAG 96 480 pot_divided-1 FLAG 352 512 inv-1 FLAG 352 608 non_inv-1 SYMBOL ind -400 -368 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 39 60 56 VTop 2 SYMATTR InstName L1 SYMATTR Value 47µ SYMATTR SpiceLine Rser=1m SYMBOL cap -384 -288 R0 WINDOW 39 -24 82 Left 2 SYMATTR SpiceLine Rser=20m SYMATTR InstName C1 SYMATTR Value 1m SYMBOL res -256 -304 R0 SYMATTR InstName R1 SYMATTR Value 5R SYMBOL res 96 -352 M0 SYMATTR InstName R3 SYMATTR Value 8k SYMBOL res 96 -192 M0 SYMATTR InstName R4 SYMATTR Value 2k SYMBOL res 176 -240 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL cap 496 -384 M90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 47n SYMBOL res 368 -384 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL voltage -800 -304 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value ac 1. SYMBOL bv 992 -240 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=5*V(error) SYMATTR InstName B1 SYMBOL bv 576 -160 M0 WINDOW 3 -195 111 Left 2 SYMATTR Value V=1E6*(V(non_inv)-V(inv)) SYMATTR InstName B2 SYMBOL res 368 -112 M0 SYMATTR InstName R7 SYMATTR Value 1m SYMBOL ind -576 368 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 39 60 56 VTop 2 SYMATTR InstName L2 SYMATTR Value 47µ SYMATTR SpiceLine Rser=1m SYMBOL cap -464 448 R0 WINDOW 39 -33 82 Left 2 SYMATTR SpiceLine Rser=20m SYMATTR InstName C2 SYMATTR Value 1m SYMBOL res -240 432 R0 SYMATTR InstName R2 SYMATTR Value 5R SYMBOL res 48 384 M0 SYMATTR InstName R8 SYMATTR Value 8k SYMBOL res 48 544 M0 SYMATTR InstName R9 SYMATTR Value 2k SYMBOL res 128 496 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value 10k SYMBOL cap 448 352 M90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 4.7n SYMBOL res 320 352 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R11 SYMATTR Value 100k SYMBOL voltage -800 432 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value ac 1. SYMBOL bv 944 496 M0 WINDOW 3 -90 113 Left 2 SYMATTR Value V=5*V(error-1) SYMATTR InstName B3 SYMBOL bv 528 576 M0 WINDOW 3 -195 111 Left 2 SYMATTR Value V=1E6*(V(non_inv-1)-V(inv-1)) SYMATTR InstName B4 SYMBOL res 320 624 M0 SYMATTR InstName R12 SYMATTR Value 1m SYMBOL cap -368 608 R0 SYMATTR InstName C5 SYMATTR Value 3m SYMBOL res -368 448 R0 SYMATTR InstName R13 SYMATTR Value 0.2R TEXT -552 -1520 Left 5 ;Simple buck, control loop response. TEXT -768 856 Left 2 !.ac dec 100 10 100k TEXT -688 -488 Left 4 ;LC filter and load TEXT -64 -496 Left 4 ;potential divider and error amp TEXT 880 -416 Left 2 ;this is calculated as \nsupply volts / (p-p sawtooth Volts)\n=10V / 2V = 5. TEXT -80 -600 Left 5 ;Development control loop TEXT -104 160 Left 5 ;Finished control loop TEXT -672 248 Left 4 ;LC filter and load TEXT -8 232 Left 4 ;potential divider and error amp TEXT 872 192 Left 4 ;supply volts\n/p-p sawtooth Volts TEXT 1272 320 Right 2 ;this voltage gain of 5 is from\nthe input voltage divided by\nthe peak to peak sawtooth Voltage TEXT -832 -1424 Left 4 ;Instructions TEXT 544 -1360 Left 2 ;The gain margin is the amount that the loop gain is less than unity (0dbs) at any freq where the loop phase is 0 degrees.\nThe phase margin is the phase angle of the loop at the freq where the loop gain goes through unity (0dbs).\nWe expect a gain margin of at least 6dbs, and a phase margin of at least 20 degrees,\notherwise we have constructed something which is uncomfortably close to being an oscillator .... \n... an oscillator wants unity gain, and zero phase shift around the loop, we want to steer clear of this \nor the circuit is liable to burst into oscillation, or at least start ringing after any load or supply transients. TEXT 520 -1408 Left 4 ;Gain margin, and phase margin. TEXT -832 -1368 Left 2 ;click on run\nclick on "development_loop_out".\nclick on "finished_loop_out".\n \nThe results from the the "Development control loop" sim shows two problems.\nThe peak in the response of the LC filter which could cause ringing or oscillations at 750hz,\nthis requires to be damped.\nThe loop does not have enough bandwidth, this will make the power supply respond slowly to transients, \nso the resulting output voltage transients will be larger and last longer. \n \nFor the damping... \n...in parrallel with the output capacitor, add a larger capacitor with a resistor in series\nthe convention is to add 3 times the present value of C, \nthe additional R in series is the impedance of the inductor at the 750hz resonant freq, of the LC, this is 0.22R\nadding this has removed the peaky response of the LC filter.\n \nFor the increase in loop gain...\nin order to increase the bandwidth of the control loop increase the output R and C impedances by a factor of 10.\n \nNow check that hte control loop is stable, so that it won't oscillate or ring.\nthat is check what the phase is when the gain goes through 0db, this is called the phase margin, this should be at least 25 degrees.\nif the phase goes through zero then check how much below 0dbs the gain is at this point, this is called the phase margin.\nfor this example the phase margin is about 26 degrees, you would not want it to be any less than this.\nthere is no gain margin as the phase does not go through 0 degrees. TEXT 528 -1168 Left 4 ;Constructing the control loop response circuit. TEXT 848 -568 Left 4 ;Loop gain\nfrom error volts to\nPWM at supply voltage TEXT 536 -1112 Left 2 ;To find the control loop gain, you start at one point of the circuit and continue all of the way around the control loop \nincluding everything that affects control loop gain or phase.\nI have started at the input to the LC filter, \nthen the output voltage potential divider, and the error amp.\nthen a block representing the gain of the pwm generation, and the supply voltage.\nthis last block cannot be the real circuit as the Spice frequency response function cannot cope with PWM switching.\n \nit is important to include the equivalent series resistance (ESR) of the electrolytic output filter cpacitors.\nother parasitic elements can also be included but the ESr of the output capacitors tends to have a greater significance. TEXT 584 880 Left 1 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. LINE Normal 528 -304 528 -304 2 LINE Normal 480 432 480 432 2 RECTANGLE Normal -144 80 -688 -464 2 RECTANGLE Normal 720 80 0 -464 2 RECTANGLE Normal 1344 112 832 -464 2 RECTANGLE Normal -144 800 -720 272 2 RECTANGLE Normal 672 800 -32 256 2 RECTANGLE Normal 1344 832 800 256 2