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128 1040 WIRE 160 1040 144 1040 WIRE 512 1040 512 992 WIRE -16 1072 -16 1040 WIRE 208 1072 208 1008 WIRE -368 1104 -368 1088 WIRE 1088 1104 1008 1104 WIRE 1312 1104 1184 1104 WIRE 928 1136 928 1104 WIRE 1008 1136 1008 1104 WIRE 1008 1136 928 1136 WIRE 144 1152 144 1040 WIRE 160 1152 144 1152 WIRE 1312 1152 1312 1104 WIRE 1344 1152 1312 1152 WIRE 1360 1152 1360 1104 WIRE 1360 1152 1344 1152 WIRE -16 1184 -16 1152 WIRE 208 1184 208 1168 WIRE 208 1184 -16 1184 WIRE 288 1184 208 1184 WIRE 512 1184 512 1104 WIRE 512 1184 288 1184 WIRE 1008 1184 1008 1136 WIRE 1008 1184 512 1184 WIRE 1344 1184 1344 1152 WIRE 288 1248 288 1184 FLAG -272 384 0 FLAG 288 1248 0 FLAG 176 144 V_supply FLAG 944 800 Cres FLAG 272 736 FET_center FLAG 576 736 Lres FLAG -832 992 0 FLAG -880 592 0 FLAG -784 480 5V FLAG -544 656 2 FLAG -544 880 3 FLAG 144 400 upper_gate FLAG 144 1008 lower_gate FLAG -928 768 test FLAG -368 832 0 FLAG -368 1104 0 FLAG -240 752 0 FLAG -240 976 0 FLAG -320 720 2_delay FLAG -320 992 3_delay FLAG -16 672 hi_drive FLAG -32 896 lo_drive FLAG -1040 912 0 FLAG 944 976 V_R_Load_pri FLAG 1344 1184 0 FLAG 1344 944 V_R_Load SYMBOL bv -32 464 R0 SYMATTR InstName B8 SYMATTR Value V=2*V(hi_drive) SYMBOL bv -16 1056 R0 SYMATTR InstName B9 SYMATTR Value V=2*V(lo_drive) SYMBOL res 128 432 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 5R SYMBOL res 144 1024 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 5R SYMBOL voltage -272 160 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value PULSE(0 48 1u 10u 1 10 20) SYMBOL res -192 128 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R_I_sense_in SYMATTR Value 1m SYMBOL res 192 320 R0 SYMATTR InstName RS1 SYMATTR Value 1m SYMBOL res 192 912 R0 SYMATTR InstName RS2 SYMATTR Value 1m SYMBOL res 832 720 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rpri_sense SYMATTR Value 1m SYMBOL ind 384 720 M90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L_res SYMATTR Value 800nH SYMATTR SpiceLine Rser=1m SYMBOL cap 496 1040 R0 SYMATTR InstName C6 SYMATTR Value 220p SYMBOL res 496 896 R0 SYMATTR InstName R15 SYMATTR Value 2R SYMBOL res 1344 1008 R0 SYMATTR InstName R_Load SYMATTR Value 30R SYMBOL cap 1024 944 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C_res SYMATTR Value 680pF SYMBOL Comparators\\LT1719 -704 592 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1719 -704 816 R0 SYMATTR InstName U2 SYMBOL voltage -880 480 R0 SYMATTR InstName V1 SYMATTR Value 5V SYMBOL nmos 160 464 R0 SYMATTR InstName X1 SYMATTR Value IPD78CN10N_L1 SYMATTR Prefix X SYMBOL nmos 160 1072 R0 SYMATTR InstName X2 SYMATTR Value IPD78CN10N_L1 SYMATTR Prefix X SYMBOL res -400 704 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 220R SYMBOL res -384 976 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 220R SYMBOL cap -384 752 R0 SYMATTR InstName C3 SYMATTR Value 100p SYMBOL cap -384 1024 R0 SYMATTR InstName C5 SYMATTR Value 100p SYMBOL Digital\\and -192 624 R0 WINDOW 3 -65 0 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A1 SYMBOL Digital\\and -192 848 R0 WINDOW 3 -55 -2 Left 2 WINDOW 123 16 52 Left 2 SYMATTR Value Vhigh=5 SYMATTR Value2 Trise=2n SYMATTR InstName A3 SYMBOL voltage -1040 784 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value SINE(0 1 7E6) SYMBOL ind 1072 1008 R0 SYMATTR InstName L1 SYMATTR Value 10m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL ind 1168 1008 R0 SYMATTR InstName L2 SYMATTR Value 90m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL res 944 1120 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R1000 SYMATTR Value 100Meg TEXT -1024 1400 Left 2 !.model pwr_diode D(Ron=1m Roff=1Meg Vfwd=.4) TEXT -1008 1360 Left 2 !.tran 0 100u 50u 10n TEXT -1024 1464 Left 2 !.model Sw_kw1 SW(Ron=.01 Roff=100Meg Vt=4 Vh=-1) TEXT -968 -1192 Left 5 ;Fixed frequency Class D amplifier, 7Mhz, supply Volts = 48V, max power about 100W. TEXT 1080 976 Left 2 !k1 L1 L2 1 TEXT 1080 800 Left 3 ;power \ntransformer TEXT 1072 880 Left 2 ;turns ratio is 1:3\nso inductance \nratio is 1:9 TEXT 768 1224 Left 2 ;the resistance that appears at the transformer primary \nis R_Load/ turns ratio squared,\n= 45 Ohms/(3 squared) = 45/9 = 5 Ohms TEXT -1024 -560 Left 2 ;click on run\nthen click on "2_out" to plot its Voltage\nthen click on "3_out" to plot its Voltage \nZoom in on the time axis to see the individual pulses.\nthese signals turn on the upper FET then the lower FET, one at a time.\nclick on the plot window, then on plot settings/add plot pane.\nthen click on "FET_center" to plot its Voltage\n \nclick on the plot window, then on plot settings/add plot pane.\nthen click on "V_R_Load_pri" to plot its voltage\nnote that "FET_center" was a square wave, and that "V_R_Load_pri" is a sine wave.\nL_res and C_res resonate the frequency that we are driving the FETs at.\n \nthen click on "V_R_Load" to plot its Voltage.\nthe transformer has a turns ratio of 1:3, so "V_R_Load" is 3 times "V_R_Load_pri".\nclick on the plot window, then on plot settings/add plot pane.\nclick on the circuit, press and hold the alt key, hover the mouse over R_Load and click.\nthis will plot the power out.\npress and hold the CTRL key, in the graph window click on "V(V_R_Load)*I(R_Load)"\na window will appear giving average power out.\n \nclick on the plot window, then on "View /FFT" in the top toolbar, then on "V(v-r_load)"\nthis will plot its FFT. TEXT -1032 -608 Left 5 ;Instructions, first level TEXT 1736 -1176 Left 2 !**********\n.SUBCKT IPD78CN10N_L1 drain gate source PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=2.5n Ld=1n Lg=3n\n \n.PARAM Rs=3.14m Rg=0.8 Rd=50u Rm=660u\n.PARAM Inn=13 Unn=10 Rmax=78m gmin=6.5\n.PARAM act=1.238\n \nX1 d1 g s Tj S3_100_a_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn} \n +Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm} heat=0\nRg g1 g {Rg} \nLg gate g1 {Lg*if(dgfs==99,0,1)}\nGs s1 s VALUE={V(s1,s)/(Rs*(1+(limit(V(Tj),-200,999)-25)*4m)-Rm)}\nRsa s1 s 1Meg\nLs source s1 {Ls*if(dgfs==99,0,1)}\nRda d1 d2 {Rd}\nLd drain d2 {Ld*if(dgfs==99,0,1)}\n \nE1 Tj w VALUE={TEMP}\nR1 w 0 1u\n.ENDS\n********** TEXT 1736 -552 Left 2 !.SUBCKT S3_100_a_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1 Unn=1 Rmax=1\n+gmin=1 Rs=1 Rp=1 dC=0 Rm=1u heat=0\n \n.PARAM Fm=0.065 Fn=0.5 kbq=85.8u\n.PARAM c=1.55 muc=0.0 Vth0=4.073 auth=5.5m al=0.001\n.PARAM UT=100m ab=78.7m ab2=0 lB=-23 UB=132\n \n.PARAM b0=22.55 p0=6.62 p1=-20.6m p2=39.2u\n \n.PARAM Rd=60m nmu=2.75 Tref=298 T0=273 lnIsj=-25.7\n.PARAM ndi=1.17 Rdi=12m nmu2=0.3 ta=30n td=100n\n.PARAM Rf=0.34 nmu3=1.8 rpa=150u\n \n.PARAM f3=380p f3a=60p \n.PARAM ps1=45p ps2=-62.5m ps3=80p ps4=-2 ps5=1.06p ps6=4p\n.PARAM qs1=26p qs2=50p qs3=-2 qs4=175p qs5=-0.0357 \n \n.PARAM Vmin=3.073 Vmax=5.073 dCmax=0.33\n.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)}\n.PARAM q0={b0*((T0/Tref)**nmu3)*a}\n.PARAM q1={(Unn-Inn*Rs-Vth0)*q0}\n.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0}\n.PARAM Rlim={(q1+2*q2*Rmax-SQRT(q1**2+4*q2))/(2*q2)}\n.PARAM dRd={Rd/a+if(dVth==0,limit(dR,0,1)*max(Rlim-Rd/a-Rs-Rp,0),0)}\n.PARAM bm={c/((1/gmin-Rs)**2*Inn*a*(T0/Tref)**nmu3)}\n.PARAM bet={b0+(b0-bm)*if(dR==0,if(dVth==0,limit(dgfs,-1,0),0),0)}\n.PARAM dC1={1+dCmax*limit(dC,0,1)}\n \n.PARAM Cox1={ps1*a*dC1}\n.PARAM Cox2={ps3*a*dC1}\n.PARAM Cox3={(ps5*a+ps6)*dC1}\n.PARAM Cds0={qs1*a*dC1}\n.PARAM Cds1={qs2*a*dC1}\n.PARAM Cds2={qs4*a*dC1}\n.PARAM Cgs0={(f3a+f3*a)*dC1}\n.PARAM dRdi={Rdi/a}\n \n.FUNC I0(Uee,p,pp,z1,cc) {if(Uee>pp,(Uee-cc*z1)*z1,p*(pp-p)/cc*exp((Uee-pp)/p))}\n.FUNC Ig(Uds,T,p,Uee,cc) {bet*(T0/T)**nmu3*I0(Uee,p,min(2*p,p+cc*Uds),min(Uds,Uee/(2*cc)),cc)}\n.FUNC J(d,g,T,da,s) \n+ {a*s*((Ig(da,T,(p0+(p1+p2*T)*T)*kbq*T,g-Vth+auth*(T-Tref)+Fm*da**Fn,c*(T/Tref)**muc)+exp(min(lB+(d-UB-ab*(T-Tref))/UT,25))))}\n \n.FUNC Idiode(Usd,Tj,Iss) {exp(min(log(Iss)+Usd/(ndi*kbq*Tj),7))-Iss}\n.FUNC Idiod(Usd,Tj) {a*Idiode(Usd,Tj,exp(min(lnIsj+(Tj/Tref-1)*1.12/(ndi*kbq*Tj),7))*(Tj/Tref)**3)}\n \nE_Edg1 d ox VALUE {if(V(d,g)>0,V(d,g)-(exp(ps2*max(V(d,g),0))-1)/ps2,0)}\nC_Cdg1 ox g {Cox1}\nE_Edg2 d ox1 VALUE {if(V(d,g)>0,V(d,g)-(exp(ps4*max(V(d,g),0))-1)/ps4,0)}\nC_Cdg2 ox1 g {Cox2}\nVx d ox2 0\nC_Cdg3 ox2 g {Cox3}\n \nE_Eds d edep VALUE {(V(d,s)-I(V_sense3)/(Cds0+Cds1+Cds2))}\nC_Cds edep s {Cds0+Cds1+Cds2}\n \nC_Cgs g s {Cgs0}\n \nG_chan d s VALUE={J(V(d,s),V(g,s),T0+limit(V(Tj),-200,300),(SQRT(1+4*al*abs(V(d,s)))-1)/2/al,sgn(V(d,s)))}\nG_RMos d1 d VALUE={V(d1,d)/(Rf*dRd+(1-Rf)*dRd*((limit(V(Tj),-200,999)+T0)/Tref)**nmu)/(1+rpa*(I(V_sense)/a)**2)}\nV_sense dd d1 0\nG_diode s d3 VALUE={Idiod(V(s,d3),T0+limit(V(Tj),-200,499))}\nG_Rdio d2 d1 VALUE={V(d2,d1)/(dRdi*((limit(V(Tj),-200,999)+T0)/Tref)**nmu2)}\nV_sense2 d2 d3 0\n \nL_L001 a c {td/(ta+td)}\nR_R001 a b {1/ta}\nV_sense3 c 0 0\nE_E001 b 0 VALUE {I(V_sense2)}\nE_E002 e 0 VALUE {Cds1/qs3*(exp(qs3*max(V(d1,s),-1))-1)+Cds2/qs5*(exp(qs5*max(V(d1,s),-1))-1)+Cds0*V(d1,s)} \n \nR_R002 e c 1\nR_R003 a 0 500Meg\n \nR1 g s 1G\nRd01 d s 500Meg\nRd02 d2 s 500Meg\nRd03 d1 d 1k\n \nRmet s s0 {Rm}\n \nG_TH 0 Tj VALUE =\n+{(LIMIT(I(V_sense2)*V(d1,s)+(V(s,s0)**2)/Rm+(I(V_sense)-I(V_sense2))*V(d1,d)+\n+(I(V_sense)-I(V_sense2)-I(E_Edg1)-I(E_Edg2)-I(Vx)-I(E_Eds))*V(d,s),-10k,100k))}\n \n.ENDS\n \n********* TEXT 296 624 Left 2 ;with 7Mhz and 0.68nF \nL would be 0.76uH for resonance\nL increased to 0.8uH to cause reduced loss switching TEXT 176 -608 Left 2 ;resonance occurs at the 7Mhz driving frequency when\nC_res = 0.68nH and L_res = 0.76uH,\n \nHowever, if we operate with these values we get lossy switching of the FETs\nefficiency can be calculated as.... (power in R_load) / (48V x I(R_I_sense_in))\n= 121.8W out / (48V x 2.679A) input = 121.8W / 128.6W = 94.7%\nfor the input current you have to use the average, as the rms current counts negative currents as positive. \n \nif we increase the value of the inductor to 0.8uH \nefficiency = 101.2W out / (48V x 2.185A) = 101.2W out / 104.9w in = 96.5%\nthis is due to reduced loss switching in the FETs.\nwe have reduced these switching losses by causing the resonant circuits current to charge\nthe FETs output capacitance during the "deadtime",in practice this is increasing \nthe value of the resonant inductor to 0.8uH here.\nThis is explained in more detail in the document "reducing switching loss in a class D amplifier".\n \na couple of details here.\nThe efficiency figures here ignore several losses such as those in the inductor and transformer.\nHence you will not achieve such high efficiency in a real circuit.\nnote that the LTspice power dissipation function (achieved by pressing the alt key and hovering \nthe mouse over the component),\ndoes not function well for a complex component such as a FET. It works okay for a resistor though. TEXT 240 -664 Left 5 ;Instructions, reducing switching losses. TEXT -1008 -1056 Left 4 ;Using an infineon silicon FET, a lower current rating FET is chosen, to keep FET output capacitance low, so that fast switching is possible.\nHowever the FET should still be adequately derated.\nwith increasing the frequency the value of the resonant inductor has reduced so it will now be air cored TEXT -1096 1616 Left 2 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. TEXT 1736 -1264 Left 3 ;The below is one of Infineons Spice models for this FET.\nOther Spice models for this FET exist on the Infineon website. RECTANGLE Normal 1280 1136 1040 768 2