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-1568 2624 Cres FLAG -2144 2560 FET_center FLAG -1872 2560 Lres FLAG -1568 2800 V_R_Load_pri FLAG -1168 3008 0 FLAG -1168 2768 V_R_Load FLAG -2352 3280 0 FLAG -2352 2832 low_gate FLAG -2576 2832 low_drive FLAG -2352 2304 high_gate FLAG -2224 2272 high_drain FLAG -2560 2256 0 SYMBOL Comparators\\LT1719 -3456 2224 R0 SYMATTR InstName U1 SYMBOL Comparators\\LT1719 -3456 2448 R0 SYMATTR InstName U2 SYMBOL voltage -3632 2112 R0 SYMATTR InstName V3 SYMATTR Value 5V SYMBOL res -3152 2336 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 330R SYMBOL res -3136 2608 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 330R SYMBOL cap -3136 2384 R0 SYMATTR InstName C1 SYMATTR Value 100p SYMBOL cap -3136 2656 R0 SYMATTR InstName C2 SYMATTR Value 100p SYMBOL Digital\\and -2944 2256 R0 WINDOW 3 -65 0 Left 2 SYMATTR Value Vhigh=5 SYMATTR InstName A1 SYMBOL Digital\\and -2944 2480 R0 WINDOW 3 -55 -2 Left 2 SYMATTR Value Vhigh=5 SYMATTR InstName A2 SYMBOL voltage -3792 2416 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value SINE(0 1 1.84E6) SYMBOL res -1808 2544 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName Rpri_sense1 SYMATTR Value 1m SYMBOL ind -2064 2544 M90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L_res1 SYMATTR Value 8.5µ SYMATTR SpiceLine Rser=1m SYMBOL res -1168 2832 R0 SYMATTR InstName R_Load1 SYMATTR Value 50R SYMBOL cap -1488 2768 R180 WINDOW 0 24 56 Left 2 WINDOW 3 24 8 Left 2 SYMATTR InstName C_res1 SYMATTR Value 1n SYMBOL ind -1440 2832 R0 SYMATTR InstName L1 SYMATTR Value 10m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL ind -1344 2832 R0 SYMATTR InstName L2 SYMATTR Value 20m SYMATTR Type ind SYMATTR SpiceLine Rser=1m SYMBOL res -1568 2944 R180 WINDOW 0 36 76 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName R6 SYMATTR Value 100Meg SYMBOL res -2416 2848 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10R SYMBOL voltage -2560 2128 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 390V SYMBOL nmos -2272 2896 R0 SYMATTR InstName X1 SYMATTR Value SGT350R70GTK SYMATTR Prefix X SYMBOL nmos -2272 2368 R0 SYMATTR InstName X2 SYMATTR Value SGT350R70GTK SYMATTR Prefix X SYMBOL res -2432 2320 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 10R SYMBOL cap -1904 2864 R0 SYMATTR InstName C3 SYMATTR Value 10p SYMBOL res -1904 2720 R0 SYMATTR InstName R5 SYMATTR Value 1R SYMBOL bv -2608 3088 R0 SYMATTR InstName B1 SYMATTR Value V=1.8*V(lo_out)-3 SYMBOL bv -2608 2464 R0 SYMATTR InstName B2 SYMATTR Value V=1.8*V(hi_out)-3 SYMBOL res -2240 2128 R0 SYMATTR InstName R_high_sense SYMATTR Value 1m SYMBOL res -2240 2672 R0 SYMATTR InstName R_low_sense SYMATTR Value 1m SYMBOL res -2464 2416 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1R SYMBOL res -2464 2976 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 1R SYMBOL diode -2384 2416 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D1 SYMBOL diode -2384 2976 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D2 TEXT -872 1376 Left 2 !*****************************************************************\n***** STMicroelectronics SGT350R70GTK ***************************\n*****************************************************************\n* *\n* Models provided by STMicroelectronics are not guaranteed to *\n* fully represent all the specifications and operating *\n* characteristics of the product behavior that they reproduce. *\n* The model describes the characteristics of a typical device. *\n* In all cases, the current product data sheet contains all *\n* information to be used like final design guidelines and the *\n* only actual performance specification. *\n* Although models can be a useful tool in evaluating device *\n* performance, they cannot model exact device performance under *\n* all conditions. * \n* STMicroelectronics therefore does not assume any *\n* responsibility arising from their use. *\n* STMicroelectronics reserves the right to change models *\n* without prior notice. *\n* *\n* *\n*****************************************************************\n* REV.1.0 \n* Jun. 2025 *\n****************************************************************** \n***\n.subckt SGT350R70GTK Drainin Gatein Sourcein\n.param LeakI1=1.33 LeakI2=0.128 Dgs1=4.3e-07 Dgs2=2.6e-13 Dgs3=0.8 Dgs4=0.23\n + Ipara=1.920e+00 Rds=2.450e-01 k2=2.040e+00 k3=1.350e-01 k4=2.150e+00 k5=1.300e-01 Rds_factor=1.000e-01\n + IdsTc=4.800e-03 RdsTc=-9.067e-03 k2Tc=8.262e-04 k4Tc=1.527e-03 k5Tc=-2.320e-04 rg=9.000e+00\n***\n + Cgd1 = 2.0000e-13\n + Cgd2 = 4.0000e-14 Cgd3 = -4.0000e+02 Cgd4 = 4.0000e+01\n + Cgd5 = 1.9900e-13 Cgd6 = -1.9000e+02 Cgd7 = 1.6123e+01\n + Cgd8 = 1.2650e-11 Cgd9 = -1.0000e+01 Cgd10 = 3.0000e+01\n + Cgs1 = 4.5500e-11\n + Cgs2 = 1.1420e-10 Cgs3 = 2.2569e+00 Cgs4 = 2.2573e-01\n + Cgs5 = 2.2500e-11 Cgs6 = -1.6000e+01 Cgs7 = 3.0000e+01\n + Csd1 = 1.3000e-11\n + Csd2 = 1.9500e-11 Csd3 = -2.5000e+02 Csd4 = 6.6000e+01\n + Csd5 = 3.5250e-11 Csd6 = -7.5000e+01 Csd7 = 1.0000e+01\n***\nrd drainin drain_rd {((1-Rds_factor)*Rds*(1-RdsTc*(Temp-25)))}\nrs sourcein source_rs {(Rds_factor*Rds*(1-RdsTc*(Temp-25)))}\nrg gatein gate_rg {(rg)}\nRcsdconv drain_rd source_rs {100000Meg/LeakI1}\nRcgsconv gate_rg source_rs {100000Meg/LeakI1}\nRcgdconv gate_rg drain_rd {100000Meg/LeakI1}\ngswitch drain_rd source_rs Value {if(v(drain_rd,source_rs)>0,\n+ (Ipara*(1-IdsTc*(Temp-25))*log(1.0+exp((v(gate_rg,source_rs)-(k2*(1-k2Tc*(Temp-25))))/k3))*\n+ v(drain_rd,source_rs)/(1 + max(k4+k5*(1-k5Tc*(Temp-25))*v(gate_rg,source_rs),0.2)*v(drain_rd,source_rs))),\n+ (-Ipara*(1-IdsTc*(Temp-25))*log(1.0+exp((v(gate_rg,drain_rd)-(k2*(1-k2Tc*(Temp-25))))/k3))*\n+ v(source_rs,drain_rd)/(1 + max(k4+k5*(1-k5Tc*(Temp-25))*v(gate_rg,drain_rd),0.2)*v(source_rs,drain_rd))))}\nggsdiode gate_rg source_rs Value {if( v(gate_rg,source_rs)>10,\n+ (0.5*LeakI2/1077*(Dgs1*(exp((10.0)/Dgs3)-1)+Dgs2*(exp((10.0)/Dgs4)-1))),\n+ (0.5*LeakI2/1077*(Dgs1*(exp((v(gate_rg,source_rs))/Dgs3)-1)+Dgs2*(exp((v(gate_rg,source_rs))/Dgs4)-1))))}\nggddiode gate_rg drain_rd Value {if( v(gate_rg,drain_rd)>10,\n+ (0.5*LeakI2/1077*(Dgs1*(exp((10.0)/Dgs3)-1)+Dgs2*(exp((10.0)/Dgs4)-1))),\n+ (0.5*LeakI2/1077*(Dgs1*(exp((v(gate_rg,drain_rd))/Dgs3)-1)+Dgs2*(exp((v(gate_rg,drain_rd))/Dgs4)-1))))}\nE_GS tl_gs bl_gs gate_rg source_rs 1.0\nV_INGS 0 bl_gs 0V\nC_IGS tl_gs 0 1.0E-6\nG_GS gate_rg source_rs VALUE = {1E6*I(V_INGS)*\n+ (Cgs1 + 0.5*Cgs2/(1.0 + exp( (v(gate_rg,source_rs)-Cgs3)/Cgs4 ))*exp( (v(gate_rg,source_rs)-Cgs3)/Cgs4 ) +\n+ Cgs5/(1.0 + exp((v(source_rs,drain_rd)-Cgs6)/Cgs7))*exp((v(source_rs,drain_rd)-Cgs6)/Cgs7))}\nE_GD tl_gd bl_gd gate_rg drain_rd 1.0\nV_INGD 0 bl_gd 0V\nC_IGD tl_gd 0 1.0E-6\nG_GD gate_rg drain_rd \n+ VALUE = {1E6*I(V_INGD)*(Cgd1 + 0.5*Cgs2/(1.0 + exp((v(gate_rg,drain_rd)-Cgs3)/Cgs4))*exp((v(gate_rg,drain_rd)-Cgs3)/Cgs4) +\n+ Cgd2/(1.0 + exp((v(gate_rg,drain_rd)-Cgd3)/Cgd4))*exp((v(gate_rg,drain_rd)-Cgd3)/Cgd4) +\n+ Cgd5/(1.0 + exp((v(gate_rg,drain_rd)-Cgd6)/Cgd7))*exp((v(gate_rg,drain_rd)-Cgd6)/Cgd7) +\n+ Cgd8/(1.0 + exp((v(gate_rg,drain_rd)-Cgd9)/Cgd10))*exp((v(gate_rg,drain_rd)-Cgd9)/Cgd10))}\nE_SD tl_ds bl_ds source_rs drain_rd 1.0\nV_INSD 0 bl_ds 0V\nC_ISD tl_ds 0 1.0E-6\nG_SD source_rs drain_rd \n+ VALUE = {1E6*I(V_INSD)*(Csd1 + Csd2/(1 + exp((v(source_rs,drain_rd)-Csd3)/Csd4))*exp((v(source_rs,drain_rd)-Csd3)/Csd4) +\n+ Csd5/(1 + exp((v(source_rs,drain_rd)-Csd6)/Csd7))*exp((v(source_rs,drain_rd)-Csd6)/Csd7))}\n.ends\n*$\n***************************************************************************** TEXT -1432 2800 Left 2 !k1 L1 L2 1 TEXT -1432 2624 Left 3 ;power \ntransformer TEXT -1440 2704 Left 2 ;turns ratio is 1:3\nso inductance \nratio is 1:9 TEXT -1744 3048 Left 2 ;the resistance that appears at the transformer primary \nis R_Load/ turns ratio squared,\n= 450 Ohms/(3 squared) = 450/9 = 50 Ohms TEXT -3704 1992 Left 2 !.tran 0 120u 20u 10n TEXT -1968 2296 Left 2 ;SGT350R70GTK is a \n700 V, 270 m© typ., 6 A, e-mode PowerGaN transistor\nfrom ST TEXT -3208 504 Left 6 ;Class D power amplifier, 1.84Mhz, Vsupply=400V, GAN transistors. TEXT -3800 3416 Left 2 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence. TEXT -872 1240 Left 2 ;The below is one of ST's Spice models for this FET.\nOther Spice models for this FET exist on the ST website.\nI have swapped the "Gatein" and "Drainin" in the .subcircuit line of the model \nto make it agree with the inbuilt LTspice FET symbol. TEXT -3640 1264 Left 2 ;click on run\nthen click on "2_out" to plot its Voltage\nthen click on "3_out" to plot its Voltage \nZoom in on the time axis to see the individual pulses.\nthese signals turn on the upper FET then the lower FET, one at a time.\nclick on the plot window, then on plot settings/add plot pane.\nthen click on "FET_center" to plot its Voltage\n \nclick on the plot window, then on plot settings/add plot pane.\nthen click on "V_R_Load_pri" to plot its voltage\nnote that "FET_center" was a square wave, and that "V_R_Load_pri" is a sine wave.\nL_res and C_res resonate the frequency that we are driving the FETs at.\n \nthen click on "V_R_Load" to plot its Voltage.\nthe transformer has a turns ratio of 1:3, so "V_R_Load" is 3 times "V_R_Load_pri".\nclick on the plot window, then on plot settings/add plot pane.\nclick on the circuit, press and hold the alt key, hover the mouse over R_Load and click.\nthis will plot the power out.\npress and hold the CTRL key, in the graph window click on "V(V_R_Load)*I(R_Load)"\na window will appear giving average power out.\n \nclick on the plot window, then on "View /FFT" in the top toolbar, then on "V(v-r_load)"\nthis will plot its FFT. TEXT -3632 1184 Left 4 ;Instructions, first level TEXT -2416 1240 Left 4 ;Instructions, reducing switching losses. TEXT -3664 696 Left 4 ;A lower current rating FET is chosen, to keep FET output capacitance low, \nso that fast switching is possible.\nHowever the FET should still be adequately derated.\nAt 1.84Mhz the inductor will have either a ferrite (3F4, 3F46, and 4F1, from ferroxcube)\nor an MPP powder core from Magnetics inc. TEXT -2400 1304 Left 2 ;resonance occurs at the 1.84Mhz driving frequency when\nC_res = 1nH and L_res = 7.48uH,\n \nHowever, if we operate at resonance we get lossy switching of the FETs, \nwe can reduce these switching losses by causing the resonant circuits current to charge\nthe FETs output capacitance during the "deadtime",in practice this means increasing \nthe value of the resonant inductor to 8.5uH.\nThis is explained in more detail in "reducing switching loss in a class D amplifier".\n \na couple of details here.\nThe efficiency figures here ignore several losses such as those in the inductor and transformer.\nHence you will not achieve such high efficiency in a real circuit.\nnote that the LTspice power dissipation function (achieved by pressing the alt key and hovering \nthe mouse over the component),\ndoes not function well for a complex component such as a FET. It works okay for a resistor though. TEXT -2088 2440 Left 2 ;with 1.84Mhz and 1nF \nL would be 7.5uH for resonance\nL increased to 8.5uH to cause reduced loss switching TEXT -2400 1792 Left 2 ;At resonance efficiency calculated as.... (power in R_load) / (390V x I(R_sense_in))\n= 1.191kW out / (390V x 3.0995A) input = 1.191kW / 1.209kW = 98.5%\n \nIncreased inductor value, efficiency calculated as.... (power in R_load) / (390V x I(R_sense_in))\n= 988.2W out / (390V x 2.565A) input = 988.2W / 1.0004kW = 98.8% RECTANGLE Normal -1232 2960 -1472 2592 2