Version 4.1
SHEET 1 2108 680
WIRE 1408 -208 1408 -240
WIRE -32 -160 -32 -192
WIRE 384 -128 224 -128
WIRE 384 -96 384 -128
WIRE 1408 -80 1408 -128
WIRE -672 -32 -848 -32
WIRE -576 -32 -672 -32
WIRE -464 -32 -496 -32
WIRE -336 -32 -464 -32
WIRE -32 -32 -32 -80
WIRE 1408 -32 1408 -80
WIRE -848 0 -848 -32
WIRE -464 16 -464 -32
WIRE 160 16 96 16
WIRE 224 16 224 -128
WIRE 224 16 160 16
WIRE 384 16 384 -16
WIRE -336 64 -336 -32
WIRE -288 64 -336 64
WIRE -224 64 -288 64
WIRE 144 64 96 64
WIRE -848 112 -848 80
WIRE 144 112 96 112
WIRE 768 112 144 112
WIRE 1120 112 848 112
WIRE 1280 112 1120 112
WIRE 1760 112 1648 112
WIRE 1840 112 1760 112
WIRE 1920 112 1840 112
WIRE -464 144 -464 80
WIRE -416 144 -464 144
WIRE 1760 144 1760 112
WIRE -416 160 -416 144
WIRE -288 160 -336 160
WIRE -224 160 -288 160
WIRE 1920 160 1920 112
WIRE -336 208 -336 160
WIRE 160 208 96 208
WIRE -848 224 -848 192
WIRE 160 256 160 208
WIRE 1760 272 1760 224
WIRE 1920 272 1920 224
WIRE -32 288 -32 256
WIRE 1408 288 1408 256
WIRE -336 352 -336 288
WIRE 160 368 160 336
FLAG -32 288 0
FLAG 160 368 0
FLAG 384 16 0
FLAG -32 -192 0
FLAG -288 64 vIN+
FLAG -288 160 vIN-
FLAG 144 112 VOrti
FLAG -672 -32 input+
FLAG -416 160 0
FLAG -848 224 0
FLAG 144 64 VOrto
FLAG 160 16 CNV
FLAG 1840 112 vOUT
FLAG 1120 112 vDAC
FLAG 1408 -240 0
FLAG 1408 288 0
FLAG 1760 272 0
FLAG 1920 272 0
FLAG 1408 -80 Vdd
FLAG -336 352 0
SYMBOL voltage 160 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 16 105 Left 2
SYMATTR Value PWL(30n 0 40n 1.8)
SYMATTR InstName V1
SYMBOL voltage 384 -112 R0
WINDOW 0 28 -5 Top 2
WINDOW 3 23 97 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1.8 1u 10n 10n 20n 1u)
SYMBOL voltage -32 -64 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL cap -480 16 R0
SYMATTR InstName Cfilt1
SYMATTR Value 1n
SYMBOL res -592 -48 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt1
SYMATTR Value 75
SYMBOL res -320 304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Rfilt2
SYMATTR Value 75
SYMBOL AD4050 0 112 R0
SYMATTR InstName U1
SYMBOL res 1744 128 R0
SYMATTR InstName RLOAD1
SYMATTR Value 1k
SYMBOL cap 1904 160 R0
SYMATTR InstName CLOAD1
SYMATTR Value 10n
SYMBOL voltage 1408 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL AD5671R 1440 112 R0
SYMATTR InstName U2
SYMATTR SpiceLine Gain=1
SYMBOL res 864 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100R
SYMBOL voltage -848 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 1
SYMBOL voltage -848 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value SINE(0 0.0025 1k)
TEXT -848 -208 Left 2 ;Notes:\n \nVOrti: Analog output \nVOrto: "Digital" representation of the input
TEXT 1488 312 Left 2 !.tran 0 2.1m 0.1m
TEXT 72 -328 Left 2 ;LTspice shows a voltage ampliude here,....\nhowever, inside this block in reality there would be no voltage, only a set of 0's and 1s representing that voltage\nthe voltage represted can only take certain values, in this case those values are 1.25mV apart.
TEXT 1488 -168 Left 2 ;It appears that the AD5671 \nis not clocked.
TEXT -880 -768 Left 2 ;click on run\nclick on the net "input+"\nclick on the plot window, then click on plot settings/add plot pane.\nthen click on the "CNV" net, this is the clock input to the ADC,\nfor the 1khz input used here the clock input is so fast that it appears continuously sampled.\nclick on the plot window, then click on plot settings/add plot pane.\nthen click on the "Vorti" net, this is the output of the ADC\nas the input signal is low amplitude, quantisation of it means that you get steps in the output voltage.\nI have deliberately used a low amplitude AC signal here, so that you can see the quantisation.\n \nright click on component V5, in the opening window incease amplitude by x10\nrun the simulation again, \nnote the affec t of quantisation causing steps in the output voltage is much reduced.
TEXT -880 -816 Left 4 ;Instructions
TEXT -144 -280 Left 4 ;ADC
TEXT 1376 -312 Left 4 ;DAC
TEXT 368 -744 Left 2 ;The symbol for the AD4050 on the left is rather confusing... \nIt has its arrow shape pointing towards its input rather than its output.\nNote that, as we are operating with an Audio (low freq) signal, we don't see any time delay affects.\nThe only distortion we see here is due to Quantisation, which is the continuously\nvarying analogue signal being forced to take the closest digital value.
TEXT -24 -920 Left 5 ;Audio frequency A to D and D to A.
TEXT 368 -800 Left 4 ;Description
TEXT -120 -864 Left 2 ;The AD4050 (A to D converter) and the AD5671R (D to A converter) symbols/functions are inbuilt parts in LTspice.
TEXT -832 424 Left 1 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence.
RECTANGLE Normal 1328 400 64 -352 2