Version 4.1 SHEET 1 880 756 WIRE -320 -304 -784 -304 WIRE -1712 -272 -1760 -272 WIRE -1584 -272 -1632 -272 WIRE -1408 -272 -1456 -272 WIRE -1280 -272 -1328 -272 WIRE -416 -256 -608 -256 WIRE -784 -240 -784 -304 WIRE -608 -240 -608 -256 WIRE -2272 -208 -2320 -208 WIRE -2096 -208 -2192 -208 WIRE -416 -208 -416 -256 WIRE -320 -208 -320 -304 WIRE -1584 -192 -1584 -272 WIRE -1456 -192 -1456 -272 WIRE -1232 -192 -1232 -224 WIRE 96 -160 -192 -160 WIRE -2096 -144 -2096 -208 WIRE -1888 -144 -2096 -144 WIRE -1696 -144 -1888 -144 WIRE -784 -144 -784 -160 WIRE -608 -144 -608 -160 WIRE -1232 -112 -1232 -128 WIRE -1232 -112 -1344 -112 WIRE -1888 -96 -2096 -96 WIRE -1696 -96 -1888 -96 WIRE 96 -64 96 -160 WIRE 96 -64 -128 -64 WIRE -2272 -32 -2320 -32 WIRE -2096 -32 -2096 -96 WIRE -2096 -32 -2192 -32 WIRE -1840 -32 -1872 -32 WIRE -1696 -32 -1776 -32 WIRE -1232 -32 -1344 -32 WIRE -960 -32 -1232 -32 WIRE -560 -32 -880 -32 WIRE -480 -32 -560 -32 WIRE 48 -32 -112 -32 WIRE 96 -32 96 -64 WIRE 96 -32 48 -32 WIRE -1232 -16 -1232 -32 WIRE -2016 32 -2048 32 WIRE -1888 32 -1936 32 WIRE -1696 32 -1888 32 WIRE -64 48 -160 48 WIRE 96 48 96 -32 WIRE 96 48 0 48 WIRE -1232 64 -1232 48 WIRE -1696 96 -1760 96 WIRE -1760 128 -1760 96 WIRE 96 128 96 48 WIRE -1760 176 -1760 128 WIRE -1520 176 -1520 144 WIRE -416 192 -416 144 WIRE 96 256 96 208 WIRE -320 272 -320 144 WIRE -320 272 -416 272 WIRE -1760 288 -1760 256 WIRE -416 304 -416 272 WIRE -2032 368 -2032 352 WIRE -1520 368 -1520 352 WIRE -2032 464 -2032 448 WIRE -1520 464 -1520 448 WIRE -1584 656 -1584 624 WIRE -1440 656 -1440 624 FLAG -608 -144 0 FLAG -784 -144 0 FLAG -416 304 0 FLAG 96 256 0 FLAG -1584 656 0 FLAG 48 -32 DAC_out FLAG -1440 656 0 FLAG -560 -32 DAC_in FLAG -1520 176 0 FLAG -1232 -32 ADC_out FLAG -1232 64 0 FLAG -2320 -32 0 FLAG -2048 32 0 FLAG -2032 464 0 FLAG -1520 464 0 FLAG -1520 352 sclk2 FLAG -2032 352 sclk1 FLAG -1760 288 0 FLAG -2320 -208 0 FLAG -1760 -272 0 FLAG -1280 -272 0 FLAG -1232 -224 0 FLAG -1872 -32 0 FLAG -1888 -144 in_pos FLAG -1888 -96 in_neg FLAG -1760 128 SCLK_blanked FLAG -1888 32 CNV SYMBOL voltage -608 -256 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL voltage -784 -256 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL voltage -416 176 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value -5 SYMBOL res 80 112 R0 SYMATTR InstName R1 SYMATTR Value 1k noiseless SYMBOL voltage -1584 528 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value 2.5 SYMBOL voltage -1440 528 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value PWL(0 0 2u 0 +1n 2.5) SYMBOL cap 0 32 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10p SYMBOL AD3542R -320 -32 R0 SYMATTR InstName U1 SYMBOL voltage -1616 -272 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 -32 56 VBottom 2 WINDOW 123 -68 56 VBottom 2 WINDOW 39 -50 56 VBottom 2 SYMATTR InstName V7 SYMATTR Value PWL(0 0 .1u 5) SYMBOL cap -1248 -16 R0 SYMATTR InstName C2 SYMATTR Value 10p SYMBOL voltage -2176 -208 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Va1 SYMATTR Value SINE(2 1 500k) SYMBOL voltage -2176 -32 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 -32 56 VBottom 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName Va2 SYMATTR Value SINE(2 1 500k 0 0 180) SYMBOL voltage -1920 32 R90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V8 SYMATTR Value PULSE(0 1.8 227n .1n .1n 40n 199.5n) SYMBOL voltage -2032 352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName Vsclk1 SYMATTR Value PULSE(0 1.8 9.5n .1n .1n 4.65n 9.5n) SYMBOL bv -1760 160 R0 SYMATTR InstName Bsclk1 SYMATTR Value V=max(V(sclk1),V(sclk2)) SYMBOL voltage -1520 352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName Vsclk2 SYMATTR Value PULSE(0 1.81 11.875n .1n .1n 66.5n 199.5n) SYMBOL voltage -1424 -272 M90 WINDOW 0 -32 56 VBottom 2 WINDOW 3 32 56 VTop 2 WINDOW 123 68 56 VTop 2 WINDOW 39 50 56 VTop 2 SYMATTR InstName V9 SYMATTR Value 1.8 SYMBOL cap -1248 -128 M180 WINDOW 0 38 64 Left 2 WINDOW 3 41 41 Left 2 WINDOW 123 41 -7 Left 2 WINDOW 39 41 16 Left 2 SYMATTR InstName C3 SYMATTR Value 10µ SYMATTR Value2 ic=4.096 SYMATTR SpiceLine Rser=10m SYMBOL cap -1776 -48 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 WINDOW 123 50 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 10µ SYMATTR Value2 ic=1.25 SYMBOL LTC2311-12 -1520 -32 R0 SYMATTR InstName U2 SYMBOL res -864 -48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 1m TEXT -816 360 Left 2 ;.tran 0 5u 0 1n TEXT -816 416 Left 2 ;.noise V(Vout) V5 dec 10 0.1 1g TEXT -2240 568 Left 2 ;VDAC input should be within the range 0 to 2.5V\nRANGE_SEL should be an integer within 0 to 4 TEXT -152 -656 Left 2 ;Range RFB RANGE_SEL \n0 to 2.5V 1x 0 \n0 to 5V 1x 1\n0 to 10V 2x 2\n-5 to 5V 2x 3\n-2.5 to 7.5V 2x 4 TEXT -1336 192 Left 2 !.tran 5u TEXT -1992 144 Center 2 ;SCLK and _CNV\nare shown in timing\ndiagram on page 11\nof LTC2311-12 data sheet TEXT -1704 -432 Left 2 ;The LTC2311-12 is 12 bit and 5 MSPS TEXT -560 -384 Left 2 ;The AD3542 is 12/16 bit and descirbed as "high speed" TEXT -1040 -760 Left 4 ;Description TEXT -1096 -720 Left 2 ;the CNV pulse tells the A to D when to sample the input.\nthe voltage it samples is (Ain+)-(Ain-)\nthe SCLK train of pulses is the processing speed to covert \nthis analog sample into a digital word.\nThe sample is taken on the falling edge of the CNV pulse.\nDuring the SCLK train of pulses the digital word is generated.\nthe digital word (Vout) is output near the end of the train of pulses.\nthere is then another CNV pulse and the process starts again. TEXT -1456 -936 Left 5 ;ADC followed by DAC, RF circuit. TEXT -1536 -872 Left 2 ;The ADC's quantising delay is significant, as is it's quantising delay.\nThe delays of the DAC are less significant. TEXT -2136 -768 Left 4 ;Instructions TEXT -2296 -744 Left 2 ;click on run\nclick on the net "in_pos", then on the net "in_neg",\nby clicking on the text in ther graph wndow and using "cntrl C" and "cntrl V" \nchange V(in_pos) to V(in_pos)-V(in_neg), this is the voltage the ADC uses as its input.\nclick on the net "ADC_out" to plot it, \nnote that after "V(in_pos)-V(in_neg)" is sampled there is a delay before it becomes "ADC_out" \n \nclick on the plot window, then click on plot settings/add plot pane. TEXT -1536 -896 Left 2 ;The LTC2311-12 (A to D converter) and the AD3542R (D to A converter) symbols/functions are inbuilt parts in LTspice. TEXT -528 520 Left 1 ;You may republish or reuse this circuit implementation and text providing this line and the following lines are included.\nThis circuit implementation designed by Keith Wallbanks. Originally released on analogsimulation.co.uk\nThis circuit is provided as is without warranty of any kind. This text is intended to implement the MIT licence.